IC designers are taking power issues earlier into consideration in coming up with system-on-a-chip devices, this analysis notes. Rob Knoth of Cadence Design Systems said, "Still, there is a huge opportunity to take a design that's on the shelf, inject some new tooling in it that allows the designers to scrub the power more effectively, tape it out on the same node, and reduce the power by 25%."
Leti researchers have come up with several changes in the memory portion of system-on-a-chip devices, such as reconfiguring static random-access memory as content-addressable memory, enhancing nonvolatile crossbar memory and using tunnel field-effect transistors. Researchers also presented an IEDM paper on placing a high-density SRAM bitcell on the CoolCube 3D platform, reducing the chip area needed for memory by 30%.
Chipmakers in South Korea will spend $17.89 billion this year on new semiconductor manufacturing equipment, up from $7.69 billion in 2016, while Taiwan will increase its spending on chip by just 3.19% in 2017, to $12.62 billion, SEMI estimates. The industry trade group predicts China will overtake Taiwan in equipment purchases during 2018.
As Toshiba proceeds with the sale of its memory chip business, it must come up with new ideas to replace the revenue and profits to be lost in divesting the semiconductor unit, this opinion piece asserts. "Toshiba's problem is how to develop new core businesses to replace its semiconductor operations," it notes.
Google's second-generation Tensor Processing Unit can both train and run machine-learning models on its own, rather than leaving the training to separate CPUs and graphics processing units. The company will gather 64 TPU2 chips to form a TPU Pod supercomputer for artificial intelligence and machine learning applications.
JEDEC's DDR5 DRAM specification will improve the density and bandwidth of the traditional memory technology, yet it may not suffice for the next generation of computing, industry experts say. "There is clearly a need for more memory bandwidth and more memory capacity, but DDR5 won't be enough by itself and it's not clear which of several other approaches may take off," says Steven Woo of Rambus.
JEP95 is a compilation of some 3000 pages of outline drawings for microelectronic packages. An annual updating service and complete hard copies are available for purchase in addition to the downloads available on the JEDEC website. View ordering information and recent updates on the JEP95 webpage.
STMicroelectronics and ams are posting impressive financial results in a sign of the new strength in the European semiconductor industry, Junko Yoshida writes. Apple's iPhone X includes ST's near-infrared imaging chips and ams dot illuminators.
GlobalFoundries provided details about its process for making chips with 7-nanometer features at the International Electron Devices Meeting in San Francisco. The company disclosed the 7LP process provides a fin pitch of 30nm, a gate pitch of 56nm and a minimum metal pitch of 40nm.
- Page 1